Field of the Invention
The present invention relates to a communication interface between host and peripheral device, and particularly it relates to signal synchronization in the communication interface.
Description of the Related Art
Signal synchronization is an important issue in the communication between a host and a peripheral device.
One conventional technique uses two separate paths to generate a host clock signal and a bus clock signal, both based on a source clock signal that is generally provided from an oscillator on a motherboard. The host operates according to the host clock signal. A peripheral device coupled to the host via an interface bus operates according to the bus clock signal. An additional phase-locked loop is required in the path generating the bus clock signal and a complex clock path analysis has to be performed to properly generate the host clock signal and the bus clock signal to make the host and the peripheral device communicate smoothly via the interface bus.